1. Field of the Invention
The present invention relates to an image signal processing applied to video tape recorder (hereinafter called as VTR), which is capable of reproducing a magnetic tape to which the image signal is recorded by a PAL format and an NTSC format, and more particularly to a color signal processor for inverting an R-Y axis of a chrominance signal.
2. Description of the Related Art
FIG. 11 shows a color signal processor of a conventional VTR disclosed in "Hitach Hyoron" Vol. 74 No. 3 (1992-3) p.277. An image signal recorded to a magnetic tape 1 is read by a magnetic head 2, and supplied to a color signal reproduction processor 3. One chrominance signal reproduced by the color signal reproduction processor 3 is directly supplied to a switch 5, and the other Chrominance signal is supplied to the switch 5 through a phase shifter 4. The phase shifter 4 shifts only a phase of a color burst signal on a color orthogonal two phase coordinate at -45.degree.. One output of the switch 5 is directly supplied to a switch 7, and the other output is supplied to the switch 7 through an R-Y axis inverting section 6. The R-Y axis inverting section 6 inverts the R-Y axis on the color orthogonal two phase coordinate, thereby inverting the color signal. One output signal of the switch 7 is directly supplied to a switch 9, and the other output signal is supplied to a switch 9 through a phase shifter 8. The phase shifter 8 shifts only the phase of the color burst signal on the color orthogonal two phase coordinate at +45.degree.. The switches 5, 7, and 9 are suitably changed in the following three cases:
(1) A case in which an image signal recorded by the PAL format is converted to an image signal recorded by the NTSC format (hereinafter called as PAL.fwdarw.NTSC conversion). PA1 (2) A case in which an image signal recorded by the NTSC format is converted to an image signal recorded by the PAL format (hereinafter called as NTSC.fwdarw.PAL conversion). PA1 (3) A case in which a skew generated when an image signal recorded by the
format is reproduced at a multiple speed (hereinafter called as PAL special reproduction).
FIGS. 12 to 14 show a signal of each section of the color signal processor. FIG. 12 shows the process of correcting the skew generated by a track jump every 1 H. In this case, the switch 5 always selects a signal b, the switch 7 alternately selects signals d and e every 1 H, and the switch 9 always selects a signal f.
FIG. 13 shows the process of the PAL.fwdarw.NTSC conversion every 1 H. In this case, the switch 5 always selects the signal b, the switch 7 alternately selects the signals d and e every 1 H, and the switch 9 always selects a signal g.
FIG. 14 shows the process of the NTSC.fwdarw.PAL conversion every 1 H. In this case, the switch 5 always selects a signal c, the switch 7 alternately selects the signals d and e every 1 H, and the switch 9 always selects the signal f.
FIG. 15 specifically shows the R-Y axis inverting section 6 and the switch 7. The R-Y axis inverting section 6 comprises a multiplier 12 and a frequency multiplier 13. The multiplier 12 multiplies the input signal d and an arithmetic carrier signal i together. The frequency multiplier 13 multiplies a frequency of a color subcarrier twice. The switch 7 comprises a switch 10 and a low pass filter (LPF) 11.
As an input signal d, a signal wherein amplitude is A and a phase angle .theta. to an angle frequency .omega..sub.SC corresponding to a frequency f.sub.SC of the color subcarrier is provided will be considered as follows.
More specifically, the input signal d can be expressed as the following equation (1). EQU d=A sin (.omega..sub.SC t+.theta.) (1)
In this case, .omega..sub.SC =1/2 .pi.f.sub.SC. It is noted that amplitude are expressed by capital letters A to H in the following signals.
The arithmetic carrier signal i inputted to the multiplier 12 shown in FIG. 15 can be expressed as the following equation (2). EQU i=-2 cos 2.omega..sub.SC t (2)
In this case, the output signal e of the multiplier 12 can be expressed as the following equation (3). ##EQU1##
When the switch 10, which is used to perform a color arrangement shown in FIG. 15, selects the signal e, the LPF 11 extracts a first term of the equation (3) as the output signal f. The output signal f can be expressed as the following equation (4). EQU f=A sin (.omega..sub.SC t-.theta.) (4)
Regarding the signal f expressed by the equation (4), the signal d shown in FIG. 16 is defined by +.theta. ("+" shows an anticlockwise direction) to B-Y axis, and the signal f shown in FIG. 17 is defined by -.theta. ("-" shows a clockwise direction) to B-Y axis.
When the switch 10 selects d as an output signal k, the signal d shown by the equation (1) can be obtained as the output f of the filter 11. Therefore, the processes d.fwdarw.e.fwdarw.f shown in FIGS. 12, 13, and 14 can be realized by changing the switch 7.
FIG. 18 specifically shows the color signal reproduction processor 3.
In FIG. 18, a reproduced image signal a is supplied to a low chrominance signal processor 15. The low chrominance signal processor 15 removes an unnecessary component of a chrominance signal whose frequency is converted to a low frequency outputted from the magnetic head. The low chrominance signal processor 15 sets amplitude of the chrominance signal to a certain reference level, and supplies the chrominance signal to one input side of a multiplier 16. The arithmetic carrier signal is supplied to the other input terminal through a band pass filter (BPF) 19. A band pass filter (BPF) 17 is connected to an output terminal of the multiplier 16, and a comb filter (C-COMB) 18 for chrominance signal is connected to an output terminal of the band pass filter 17.
A voltage controlling oscillator (VCO) 20 generates a signal whose frequency is 320 times larger than the frequency of a horizontal sync signal f.sub.H. The VCO 20 is connected to a divider 21. The divider 21 divides the frequency of the inputted signal to 1/8, and outputs four signals whose phases are different by 90.degree., respectively. The divider 21 is connected to a four-phase rotation circuit 22. The four-phase rotation circuit 22 sequentially outputs four signals, which are supplied from the divider 21, in accordance with control signals. The phases of these four signals differ by 90.degree.. The four-phase rotation circuit 22 is connected to one input terminal of a multiplier 23. An oscillator (OSC) 24, which generates a color subcarrier frequency f.sub.SC, is connected to the other input terminal of the multiplier 23. An output terminal of the multiplier 23 is connected to the input terminal of the BPF 19. The above example explains the VTR of a VHS format. However, in the case of the VTR of a D format, in place of the four-rotation circuit 22, a phase inverting circuit may be used. Moreover, in the case of a 8 mm format, in place of the four-phase rotation circuit 22, a phase inverting circuit in NTSC, and in the case of PAL, the four-phase rotation circuit may be used.
In order to understand the calculation processing of the multipliers 16 and 23 by a numerical expression, the output signals 1, q, r of the low chrominance signal processor 15, the four-phase rotation circuit 22, and the OSC 24 are respectively expressed as follows: EQU l=B cos (.omega..sub.L t-.theta.+.phi.) (5) EQU q=C sin (.omega..sub.L t+.theta.+.phi.) (6) EQU r=D cos .omega..sub.SC t (7)
wherein .phi.: phase angle in recording, .theta.: phase angle based on FIG. 16, .omega..sub.L =1/2.pi.f.sub.L, and f.sub.L =frequency of chrominance signal converted to low band.
In order to understand the setting of an input signal 1 of the multiplier 16 shown in the equation (5), FIG. 19 shows a simple structure of the color signal recording processing of the VTR. This circuit comprises a multiplier 25 and a low pass filter (LPF) 26.
In FIG. 19, a color signal St having a color subcarrier frequency f.sub.SC and an arithmetic carrier signal w for converting the color signal St to a low frequency can be set as follows: EQU St=E sin (.omega..sub.SC t+.theta.) (8) EQU w=F sin {(.omega..sub.SC +.omega..sub.L)t+.phi.} (9)
from equations (1) and (2), ##EQU2##
In FIG. 19, if a signal u passes through the LPF 26, only the first term of equation (10) is obtained, and a chrominance signal v can be obtained as follows. EQU v=G cos (.omega..sub.L t-.theta.+.phi.) (11)
In a case where the signal v shown in equation (11) is recorded and reproduced, the same frequency component can be obtained as a reproducing signal. The equation (11) is the same as the equation (5) excepting that amplitude differs.
Then, back to FIG. 18, an output signal p of the multiplier 23 is obtained as follows:
From equations (6) and (7), EQU p=q.times.r=DC/2 [sin {(.omega..sub.SC +.omega..sub.L)t+.phi.}-sin (.omega..sub.SC -.omega..sub.L)t-.phi.)] (12)
The second term of the equation (12) is removed by the BPF 19 of FIG. 18, and an arithmetic carrier signal o is obtained. The arithmetic carrier signal o can be expressed as follows: EQU o=H sin (.omega..sub.SC +.omega..sub.L)t+.phi.) (13)
The arithmetic carrier signal o is supplied to the multiplier 16. In the multiplier 16, the following calculation is performed.
From equations (5) and (13), ##EQU3##
The second term of the equation (14) is removed by the BPF 17 of FIG. 18, and a chrominance signal b, which is expressed by the following equation (15), can be obtained from the output terminal C-COMB 18. EQU b=I sin (.omega..sub.SC t+.theta.) (15)
The frequency and the phase expression of the chrominance signal shown by the equation (15) are the same as those of each of the signals d and t shown by the equations (1) and (8), and the chrominance signal can be expressed by the phase angle shown in FIG. 16.
In the conventional color signal processor, the color signal reproduction processor 3 shown in FIG. 11 and the R-Y inverting section 6 were needed. As described above, the arithmetic carrier signal was needed in the R-Y inverting section 6. As shown in the above equation (2), there is needed a circuit structure such that no phase difference between the signal d shown in the equation (1) and the arithmetic carrier signal i. FIG. 20 explains the specific example of the circuit structure.
In FIG. 20, an output signal of an oscillator 30 for oscillating a color subcarrier frequency f.sub.SC is supplied to the frequency multiplier 13 through a variable phase shifter 31. The frequency multiplier 13 comprises a 90.degree. phase shifting circuit 13a for inverting an output signal of the variable phase shifter 31, a multiplier 13b for multiplying the output of the variable phase shifter 31 and an output signal of the 90.degree. phase shifting circuit 13a together, and a resonator 13c in which an output of the multiplier 13b is supplied thereto and a resonation frequency, which is twice as large as the color subcarrier frequency f.sub.SC, is provided.
FIG. 21 shows the specific circuit of the variable phase shifter 31. The variable phase shifter 31 controls the phase of the input signal by use of a resonating circuit 33 connected between a collector of a transistor 32 and an emitter.
As is obvious from FIGS. 20 and 21, in the conventional color signal processor, the R-Y axis inverting section 6 includes the resonating circuit. Due to this, the circuit structure was complicated, and not suitable for the integrated circuit.